Stanford
Shriram Family Director, Knight-Hennessy Scholars John L. Hennessy

Curriculum Vitae – John L. Hennessy

Education

  • Ph.D. Computer Science, S.U.N.Y. Stony Brook, 1977
  • M.S. Computer Science, S.U.N.Y. Stony Brook, 1975
  • B.E. Electrical Engineering, Villanova University, 1973

Professional Experience

9/2016 – presentDirector, Knight-Hennessy Scholars Program
9/2000 – 8/2016President, Stanford University
6/1999 – 8/2000Provost, Stanford University
6/1996 – 6/1999Dean, School of Engineering, Stanford University
9/1994 – 3/1996Chairman, Department of Computer Science, Stanford University
9/1986 – presentProfessor of Electrical Engineering and Computer Science, Stanford University
6/1992 – 6/1998Chief Architect, Silicon Graphics Computer Systems
9/1984 – 6/1992Cofounder & Chief Scientist, MIPS Computer Systems (now part of Imagination Tech.)
9/1983 – 9/1986Associate Professor of Electrical Engineering, Stanford University
9/1977 – 9/1983Assistant Professor of Electrical Engineering, Stanford University

Academic, Technical, and Leadership Awards and Honors

  • Charles Stark Draper Prize for Engineering (co-winner), 2022.
  • BBVA Foundation Frontiers of Knowledge Award in Information and Communication Technologies (jointly with D. Patterson), 2021.
  • ACM A.M. Turing Award (jointly with D. Patterson), 2017.
  • Doctor of Humane Letters (honorary), Indiana University, 2018.
  • Distinguished Citizen Award, Commonwealth Club, San Francisco, 2018.
  • Fellow of the Royal Academy of Engineering, United Kingdom, Elected 2017.
  • Legendary Leader, Churchill Club, Silicon Valley, 2017.
  • Okawa Prize for Information and Telecommunications, 2017.
  • Honorary Doctorate, University of Strathclyde, 2016.
  • James F. and Mary Lynn Gibbons Endowed Professor of Computer Science and Electrical Engineering, 2016.
  • The Frank E. Taplin, Jr. Public Intellectual Award. The Woodrow Wilson National Fellowship Foundation, 2016.
  • Honorary Doctor of Education, University of San Francisco, 2015.
  • Exemplary Leader Award, American Leadership Forum, Silicon Valley, 2014.
  • Carnegie Academic Leadership Award, Carnegie Foundation, 2013.
  • Tall Tree Global Impact Award, Palo Alto Chamber of Commerce, 2013.
  •  Doctor Honris Causa, Mathematics, University of Waterloo, 2012.
  • IEEE Medal of Honor (Highest award given by the Institute of Electrical and Electronics Engineers), 2012
  • Morris Chang Exemplary Leadership Award, Global Semiconductor Alliance, 2010.
  • Foreign Policy Association Medal and Honorary Fellow, Foreign Policy Association, 2010
  • Ulysses Medal, University College Dublin, 2009.
  • Spirit of Silicon Valley—Lifetime Achievement Award, Silicon Valley Leadership Group, 2009
  • Member, American Philosophical Society, 2008.
  • Fellow, Computer History Museum, 2007.
  • Founders Award, American Academy of Arts and Sciences, 2005.
  • 100th Anniversary Medallion, College of Engineering, Villanova University, 2005.
  • Honorary Doctorate, University of Edinburgh University, 2005.
  • NEC Computers and Communications Prize, 2004.
  • Honorary Doctor Degree, Peking University, 2004.
  • Honorary Doctor of Engineering, University of Notre Dame, 2004
  • Docteur Honris Causa, Ecole Polytechnique Federale de Lausanne, 2003
  • Member, National Academy of Sciences, 2002
  • Doctor Honris Causa, Universitat Politècnica de Catalunya, 2002
  • Seymour Cray, Computer Engineering Award, 2001
  • Eckert-Mauchly Award, Association for Computing Machinery and IEEE Computer Society, 2001
  • Honorary Doctor of Science, State University of New York at Stony Brook, May 2001
  • Honorary Doctor of Humane Letters, Villanova University, May 2001
  • John Von Neumann Medal (jointly with D. Patterson), IEEE, 2000
  • Benjamin Garver Lamme Award, American Society for Engineering Education, 2000.
  • Corresponding Member, Royal Academy of Engineering, Spain
  • J. Stanley Morehouse Memorial Award, Villanova University, 1997
  • Fellow, Association for Computing Machinery, 1997.
  • Fellow, American Academy of Arts and Sciences, 1995.
  • IEEE Emannuel R. Piore Award, 1994.
  • Member, National Academy of Engineering, 1992.
  • Fellow, Institute of Electrical and Electronics Engineers, 1991.
  • Distinguished Alumnus Award, State University of New York at Stony Brook, 1991.
  • Willard and Inez Kerr Bell Endowed Professor of Electrical Engineering and Computer Science, 1987.
  • Presidential Young Investigator, National Science Foundation, 1984.
  • John J. Gallen Memorial Award, Villanova University, 1983.
  • Honorary Societies: Tau Beta Pi, Eta Kappa Nu, Pi Mu Epsilon, 1973.

Corporate and Advisory Boards

  • Google, Board of Directors, April 2004-present, Chair 2018-present.
  • Cisco Systems, Board of Directors, January 2002-2018.
  • Founding Chairman, Board of Directors, Atheros (now part of Qualcomm), 1998-2010.
  • Technology Advisory Board, Microsoft Corporation, 1992-96.

Public Service and Nonprofit Activities

  • Member, Strategic Council on Research Excellence, Integrity, and Trust, National Academy of Sciences, 2021-2024.
  • Board of Directors, Chan Zuckerberg Biohub, 2015-2024.
  • Board of Trustees, Gordon and Betty Moore Foundation, 2012-present.
  • Member, Committee on Research Universities, National Research Council, 2010-2012.
  • Co-chair, Committee on Scientific Communication and National Security, National Research Council, 2007-2009.
  • Member, Member, National Academy of Engineering, Peer Selection Committee for Computer Science and Engineering, 1996-1999, Chair (2000).
  • Member, Committee to Study the Investment Strategy for DARPA, Defense Science Board, 1998-99.
  • Member, Commission on Physical Sciences, Mathematics, and Applications, National Research Council, 1998-99.
  • Chairman, Information Science and Technology (ISAT) Study, Defense Advanced Research Projects Agency, 1994-96, Chair (1994-95).
  • Member, Task Force on Future of Supercomputer Centers Program, National Science Foundation, 1995.
  • Member, Status and Direction of the High Performance Computing and Communications Initiative (Brooks-Sutherland Committee), National Research Council, 1995.
  • Member, Advisory Committee for Computer and Information Science and Engineering, NSF, 1992-96.
  • Member, Computer Science and Technology Board, National Research Council, 1989-94.
  • Member, Fellowship Selection Committee, Sloan Foundation, 1993-96.
  • Member, Committee to Study Academic Careers for Experimental Computer Scientists, National Research Council, 1992-1993.
  • Chair, Oversight Review of the Computer and Information Science and Engineering Institutional Infrastructure Program, National Science Foundation, 1992.
  • Member, Committee to Study International Developments in Computer Science and Technology, National Research Council, 1988.
  • Academic Advisory Councils and Visiting Committees
    • College of Engineering, UC Berkeley
    • College of Engineering, Cornell University
    • Computer Science Department, Princeton University
    • School of Engineering and Applied Sciences, Princeton University
    • NCIR, Dublin, Ireland

Editorships and Conference Committees

  • General Chair, Program Committee Co-Chair, Program Committee Member, Hot Chips Symposium, 1999, 1993, 1991.
  • Program Chair, 20th International Conference on Computer Architecture, 1993.
  • Program Chair, ASPLOS-III Conference, 1988.
  • Member, Program Committee, 4th Annual ACM Symposium on Parallel Algorithms and Architectures, 1992.
  • Co-Chair, Research in Experimental Computer Science (sponsored by Office of Naval Research), 1991.
  • Member, Program Committee, SOSP Conference, 1991.
  • Member, Program Committee, ACM Sigmetrics Conference, 1991.
  • Member, Program Committee, ISSMM, 1991.
  • Member, Program Committee, Intl. Conference on Shared-Memory Multiprocessors, 1990.
  • Member, Program Committee, Intl. Symposium on Computer Architecture, 1986, 1987, 1990, 1995, 1999.
  • Member, Program Committee, ASPLOS-II Conference, 1987.
  • Area Editor (Parallel Architecture), Journal of Parallel and Distributed Computing.
  • Area Editor (Computer Architecture), Journal of the Association for Computing Machinery, 1990-1995.
  • Associate Editor, IEEE Transactions on Microelectronic Systems, 1992-1993.
  • Editor, Journal of the Association for Computing Machinery, 1990-1993.
  • Editor, Journal of VLSI and Computer Systems, 1982-1984.
  • Editor, IEEE Design and Test, 1984, 1985, 1986.
  • Associate Editor, IEEE MICRO, 1981, 1982.

Major Keynote and Plenary Addresses

  • Turing Award Lecture (joint with David Patterson), ISCA, Los Angeles, 2018.
  • Keynote Lecture, Ecole Polytechnique Federale de Lausanne, 150th Anniversary Celebration, 2003.
  • Keynote Lecture, Microprocessor Forum, San Jose, CA, October 1999.
  • Plenary Speaker, Federated Computer Research Conference, Atlanta, Georgia, May 1999.
  • Keynote Speaker, Intl. Symposium on Computer Architecture, Barcelona, Spain.  June 1998.
  • Keynote Speakers, APEC R&D Leaders, Forum, Tapei, March 1998.
  • Keynote Speaker, SIAM-97, 45th Anniversary Conference, Palo Alto, CA, July 1997.
  • Keynote Speaker, Symposium on Principles and Practice of Parallel Programming, Santa Barbara, CA. July 1995.
  • Keynote Speaker, VLSI ‘93 Conference, Grenoble, France. September 1993.
  • Keynote Speaker, Systems Integrated Symposium, Seattle, WA. March 1993.
  • Keynote Speaker, Parallel Processing and Distributed Systems Conference, Dallas, TX December 1992.
  • Keynote Speaker, IEEE Multi-Chip Module Conference, Santa Cruz, CA, March 1992.
  • Keynote Speaker, DECUS Forum, Anaheim, CA, December 1991.
  • Microprocessor Forum, San Jose, CA, September 1989.
  • International Conference on Measurement and Modeling of Computer Systems, ACM Sigmetrics, May 1989.
  • Caltech VLSI Conference, Pasadena, CA, March 1989.
  • IEEE Compcon, February 1988.

Distinguished Lectures

  • University Southern California, Viterbi School of Engineering Cenntennial Lecture, Department of Computer Science, February 2006.
  • Princeton University, Louis Clark Vanuxem Lecture, April 2003.
  • Technische Universiteit Eindhoven, Holst Memorial Lecture,  November 2001.
  • Eidgenössisch Technisch Hochschule, Zurich, June 1999.
  • University of Illinois, Urbana-Champaign, IL.  November 1998. Geddes Memorial Lecture.
  • Bell Laboratories, Distinguished Lecture Series, October 1998.
  • State University of New York, Stony Brook, NY.  April 1998. Fortieth Anniversary Lectures.
  • University of Minnesota, Cray Memorial Lecture,  April 1998.
  • University of California, San Diego, February 1997.
  • University of Tennessee, Oakridge, TN. March 1996.
  • University of Michigan, Ann Arbor, MI. March 1996.
  • University of Utah, Salt Lake City, UT. February 1996. Organick Memorial Lecture.
  • Carnegie-Mellon University, Pittsburgh, PA. February 1995.
  • University of California, Santa Barbara, CA. January 1995.
  • New York Courant Institute, New York, NY. October 1994.
  • University of California, Los Angeles, CA. December 1992.
  • University of Washington, Seattle, October 1992.
  • California Institute of Technology, Pasadena, CA, December 1991.
  • University of Texas, Austin, TX, December 1991.
  • Princeton University, Princeton, NJ, November 1991.
  • University of California at San Diego, San Diego, CA. April 1991.
  • Villanova University, Villanova, PA. February 1991.
  • University of Arizona, Phoenix, AZ. February 1991.
  • University of Wisconsin, Madison, WI. October 1990.
  • Digital Equipment Corporation, Cambridge, MA. July 1990.
  • Carnegie-Mellon University, Pittsburgh, PA. April 1990.
  • University of Southern California, Los Angeles, CA. April 1990.
  • Massachusetts Institute of Technology, Cambridge, MA, October 1989.
  • SUNY at Stony Brook, Stony Brook, New York, May 1989.
  • University of Illinois at Urbana-Champaign IL, May 1989.

Publications

Books and Contributions to Books

  1. Hennessy, J. L. and Patterson, D. A. Computer Architecture: A Quantitative Approach. 1990. Morgan Kaufmann Publishers, Inc. San Mateo, CA. Second edition 1995, Third edition, 2002. Fourth Edition, 2007, Fifth Edition, 2011, Sixth Edition, 2018.
  2. Patterson, D.A. and Hennessy, J.L., Computer Organization and Design: The Hardware/Software Interface. 1993. San Mateo, CA: Morgan Kaufmann Publishers. Second Edition, 1998, Third Edition 2005.
  3. Tjiang, S., Wolf, M., Lam, M., Pieper, K. and Hennessy, J. “Integrating Scalar Optimization and Parallelization.” Languages and Compilers for Parallel Computing. Banerjee ed. 1992 Springer-Verlag. New York.
  4. Acken, J., Agarwal, A., Gulak, G., Horowitz, M., McFarling, S., Richardson, S., Salz, A., Simoni, R., Stark, D. and Tjiang, S. “The MIPS-X RISC Microprocessor.” Chow ed. 1989 Kluwer Academic Publishers. Boston, MA. Foreward by J.L. Hennessy.
  5. Chow, P., Hennessy, J.L. RISC Architectures. Elsevier-North Holland, New York, 1986.
  6. Hennessy, J.L., Ganapathi, M. Advances in Compiler Technology. In Annual Review of Computer Science, Annual Reviews, Palo Alto, CA, 1986.
  7. Hennessy, J.L., Przybylski, S. VLSI Electronics. Volume VII: VLSI Design and Architecture. Academic Press, New York, 1984, chapter VLSI Processor Design Methodology.
  8. Hennessy, J.L., Kieburtz, R.B., Smith, D.R. TOMAL: A Task-Oriented Microprocessor Applications Language. In Glass, R.L. (editor), Real-Time Software, Prentice-Hall, 1982.

Refereed Journals and Conferences

For copies of recent publications see: SPLASH papers and DASH papers.

  1. Chaudhuri, M. Heinrich, M., Holt, C., Singh, J.P., Rothberg, E. and J. Hennessy “Latency, Occupancy, and Bandwidth in DSM Multiprocessors: A Performance Evaluation”. IEEE Transactions on Computers 52(7), July 2003.
  2.  Gibson, J, Kunz, R, Ofelt, D, Horowitz,M, Hennessy, J,  Heinrich, M, “FLASH vs. (Simulated) FLASH: Closing the Simulation Loop”. In Proceedings of the 9th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), pages 49-58, November 2000.
  3. Ofelt D. and Hennessy J., “Efficient Performance Prediction for Modern Microprocessors,”  Proc. of SIGMETRICS 2000, Santa Clara, CA., June 2000.
  4. Hennessy, J. “The future of systems research.” IEEE Computer Magazine, Aug. 1999. (Edited transcript of invited plenary talk at Federated Computer Research Conference, 1999.)
  5. Hennessy J, Heinrich M, Gupta A. “Cache-coherent distributed shared memory: Perspectives on its development and future challenges.”  Proc of the  IEEE, 87: (3) 418-429 Mar 1999.
  6. Heinrich M, Soundararajan V, Hennessy J, Gupta A, “A quantitative analysis of the performance and scalability of distributed shared memory cache coherence protocols.” IEEE Transactions on Computers, 48: (2) 205-217 Feb 1999.
  7.  Soundararajan, V., Heinrich M., Verghese, B., Gharachorloo, K., Gupta A., Hennessy, J. “Flexible Use of Memory for Replication/Migration in Cache-Coherent DSM Multiprocessors.”,  Proc. 25th Annual Symposium on Computer Architecture, June 1998.
  8. Thekkath, R. ,  Singh,  A. P.,  Singh, J. P.,  John, S. and J. Hennessy. “An Evaluation of a Commercial CC-NUMA Architecture- the Convex Exemplar SPP1200,” In Proceedings of the International Parallel Processing Symposium, Geneva, Switzerland, April 1997.
  9. Heinrich M, Ofelt D, Horowitz MA, Hennessy J. “Hardware/software co-design of the Stanford FLASH multiprocessor.” Proc of the  IEEE 85: (3) 455-466 Mar 1997.
  10. Erlichson, A., Nuckolls, N., Chesson, G., and Hennessy, J. “SoftFLASH: Analyzing the Performance of Clustered Distributed Virtual Shared Memory” in Seventh International Conference on Architectural Support for Programming Languages and Operating Systems. ACM/IEEE. Cambridge, MA. October 1996.
  11. Holt, C., Singh, JP, Hennessy, J. “Application and Architectural Bottlenecks in Large Scale Shared Memory Multiprocessors.” Proc. 23rd Annual Symposium on Computer Architecture, May 1996, 134-145.
  12. Singh JP, Holt C, Totsuka T, Gupta A, Hennessy J. “Load Balancing and Data Locality in Adadptive Hierarchical N-Body Methods: Barnes-Hut, Fast Multipole, and Radiosity.” Journal of Parallel and Distributed Computing, 27: (2) 118-141 June 1995.
  13. Hennessy, J.L. and Heinrich, M. “Hardware/Software Codesign of Processor Concepts and Examples” in NATO/ASI Codesign Workshop. Kluwer Publishers.Tremezzo, Italy. June 1995.
  14. Singh JP, Gupta A, Hennessy J. “Implications of Hierarchical N-body Methods for Multiprocessor Architecture.” ACM Transactions on Computer Systems, May 1995.
  15. Heinrich, M., Kuskin, J., Ofelt, D., Heinlein, J., et al. “The Performance Impact of Flexibility in the Stanford FLASH Multiprocessor” in Sixth International Conference on Architectural Support for Programming Languages and Operating Systems. ACM & IEEE. San Jose, CA. pgs. 274-285. October 1994.
  16. Woo, S., Singh, J.P., and Hennessy, J. “The Performance Advantages of Integrating Block Data Transfer in Cache-Coherent Multiprocessors” in Sixth International Conference on Architectural Support for Programming Languages and Operating Systems. ACM & IEEE. San Jose, CA. pgs. 219-230. October 1994.
  17. Torrellas, J., Lam, M.S., and Hennessy, J.L., “False Sharing and Spatial Locality in Multiprocessor Caches.” IEEE Transactions on Computers, 43: (6) 651-663 June 1994.
  18. Kuskin, J., Ofelt, D., Heinrich, M., Heinlein, J., et al. “The Stanford FLASH Multiprocessor” in 21st Annual International Symposium on Computer Architecture (ISCA). IEEE/ACM. Chicago, IL. pgs. 302-313. April 1994. Reprinted in 25 Years of ISCA: Retrospectives and Reprints, 1998.
  19. Joe, T. and Hennessy, J.L. “Evaluating the Memory Overhead Required for COMA Architectures” in 21st Annual International Symposium on Computer Architecture (ISCA). IEEE/ACM. Chicago. pgs. 82-93. April 1994.
  20. Chandra, R., Gupta, A., and Hennessy, J.L., “Integrating Concurrency and Data Abstraction in the COOL Programming Language.” IEEE Computer. February, 1994.
  21. Singh, J., Joe, T., Gupta, A., and Hennessy, J.L. “An Empirical Comparison of the Kendall Square Research KSR-1 and Stanford DASH Multiprocessors,” Supercomputing ’93. Portland, November, 1993.
  22. Singh, J.P., Holt, C., Hennessy, J.L., and Gupta, A. A Parallel Adaptive Fast Multipole Method,” Supercomputing ’93. Portland, November, 1993.
  23. Schnorf, P., Ganapathi, M., and Hennessy, J., “Compile-time Copy Elimination.” Software–Practice and Experience 23(11): pgs. 1175-1200. November.
  24. Baskett, F. and Hennessy, J., “Microprocessors: From Desktops to Supercomputers.” Science. Vol. 261: pgs. 864-871. August, 1993.
  25. Singh, J.P., Hennessy, J., and Gupta, A., “Scaling Parallel Programs for Multiprocessors: Methodology and Examples.” IEEE Computer. Vol. 26(7): pgs. 42-50. July, 1993.
  26. Schnorf, P., Ganapathi, M. and Hennessy, J.L. “Compile-time Copy Elimination.”Software Practive and E$xperion3 23(11): 1175-1200 (1993)
  27. Chandra, R., Gupta, A., and Hennessy, J. Data Locality and Load Balancing in COOL in 4th Symposium on the Principles and Practice of Parallel Programming. ACM SIGPLAN. San Diego, CA. pg. 249-259. May, 1993.
  28. Goldschmidt, S.R. and Hennessy, J.L. “The Accuracy of Trace-Driven Simulations of Multiprocessors” in SIGMETRICS Conference on Measurement and Modeling of Computer Systems. ACM. Santa Clara, CA. May 1993.
  29. Goldberg, A.J. and Hennessy, J.L., “MTOOL: An Integrated System for Performance Debugging Shared Memory Multiprocessor Applications.” IEEE Transactions on Parallel and Distributed Systems. Vol. 4(1): pgs. 28-40. January, 1993.
  30. Torrellas, J., Gupta, A., and Hennessy, J. Characterizing the Caching and Synchronization Performance of a Multiprocessor Operating System in Conference on Architectural Support for Programming Languages and Operating Systems. IEEE/ACM. Boston, MA. pg. 162-174. October, 1992.
  31. Gharachorloo, K., Adve, S., Gupta, A., Hennessy, J., et al., “Programming for Different Memory Consistency Models.” Journal of Parallel and Distributed Computing. Vol. 15(4): pgs. 399-407. August, 1992.
  32. Singh, J., Holt, C., Gupta, A. and Hennessy, J., A Parallel Adaptive Fast Multipole Method, SIAM, Society for Industrial and Applied Mathematics 40th Anniversary Conference, Los Angeles, CA. July, 1992.
  33. Chandra, R., Gupta, A. and Hennessy, J. L., Integrating Concurrency and Data Abstraction in a Parallel Programming Language, ACM SIGPLAN ’92 Conference on Programming Language Design and Implementation (PLDI), San Francisco, CA. June, 1992.
  34. Tjiang, S.W.K. and Hennessy, J. “Sharlit–A Tool for Building Optimizers”  in Proceedings of on Programming Language Design and Implementation. ACM SIGPLAN. pg. 82-93. June, 1992
  35. Singh, J. P., Hennessy, J. L. and Gupta, A., Implications of Hierarchical N-body Techniques for Multiprocessor Architecture, 19th Annual International Symposium on Computer Architecture (ISCA), Queensland, Australia. May, 1992.
  36. Lenoski, D., Laudon, J., Joe, T., Nakahira, D., Stevens, L., Gupta, A. and Hennessy, J., The DASH Prototype: Implementation and Performance, IEEE/ACM, 19th International Symposium on Computer Architecture, Queensland, Australia. pg. 92-103. May, 1992. Reprinted in 25 Years of ISCA: Retrospectives and Reprints, 1998.
  37. Gharachorloo, K., Gupta, A. and Hennessy, J., Hiding Memory Latency using Dynamic Scheduling in Shared-Memory Multiprocessors, IEEE/ACM, 19th International Symposium on Computer Architecture, Queensland, Australia. May, 1992.
  38. Singh, J.P. and Hennessy, J.L., “Finding and Exploiting Parallelism in an Ocean Simulation Program: Experiences Results, Implications.” Journal of Parallel and Distributed Computing. Vol. 15(1): pgs. 27-48. May, 1992.
  39. Lenoski, D., Laudon, J., Gharachorloo, K., Weber, W.-D., Gupta, A., Hennessy, J. L., Horowitz, M. and Lam, M. S. “The Stanford DASH Multiprocessor,” IEEE Computer. 25, (3): 63-79, March, 1992.
  40. Lenoski, D., Laudon, J., Joe, T., Nakahira, D., et al., “The DASH Prototype: Logic Overhead and Performance.” IEEE. Transactions on Parallel and Distributed Systems. Vol. 4(1): pgs. 41-61. January, 1992.
  41. Singh, J.P., and Hennessy, J.L., “Data Locality and Memory System Performance in the Parallel Simulation of Ocean Eddy Currents.”  In Proceedings of the Second International Symposium on High Performance Computing, October 1991. Also in High Performance Computing II, North-Holland, 1991.
  42. Hennessy, J. L. and Jouppi, N. P. “Computer Technology and Architecture: An Evolving Interaction,” IEEE Computer. 24, (9): 18-29, September, 1991. Special 40th Anniversary Issue.
  43. Gharachorloo, K., Gupta, A. and Hennessy, J., Two Techniques to Enhance the Performance of Memory Consistency Models, International Conference on Parallel Processing (ICPP), St. Charles, IL. August , 1991.
  44. Goldberg, A. and Hennessy, J., Performance Debugging Shared Memory Multiprocessor Programs with MTOOL, Supercomputing 91, Albuquerque, NM. 1991.
  45. Goldberg, A. and Hennessy, J., MTOOL: A Method for Isolating Memory Bottlenecks in Shared Memory Multiprocessor Programs, International Conference on Parallel Processing (ICPP), St. Charles, IL. August, 1991.
  46. Davis, H., Goldschmidt, S. R. and Hennessy, J., Multiprocessor Simulation and Tracing Using Tango, 1991 International Conference on Parallel Processing (ICPP), St. Charles, IL. August, 1991.
  47. Maydan, D. E., Hennessy, J. L. and Lam, M. S., Efficient and Exact Data Dependence Analysis, ACM SIGPLAN ’91 Conference on Programming Language Design and Implementation (PLDI), Toronto, Ontario, Canada. June, 1991.
  48. Gupta, A., Hennessy, J., Gharachorloo, K., Mowry, T. and Weber, W.-D., Comparative Evaluation of Latency Reducing and Tolerating Techniques, 18th International Symposium on Computer Architecture (ISCA), Toronto, Ontario, Canada. May, 1991.
  49. Gharachorloo, K., Gupta, A. and Hennessy, J. L., Performance Evaluation of Memory Consistency Models for Shared-Memory Multiprocessors, ACM/IEEE, Fourth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-IV), Santa Clara, CA. April, 1991.
  50. Lenoski, D., Laudon, J., Gharachorloo, K., Weber, W.-D., Gupta, A. and Hennessy, J. L., Overview and Status of the Stanford DASH Multiprocessor, ISSMM Conference, Tokyo, Japan. April, 1991.
  51. Singh, J. P. and Hennessy, J. L., An Empirical Investigation of the Effectiveness and Limitations of Automatic Parallelization, International Symposium on Shaed-Memory Multiprocessors, Tokyo, Japan. April, 1991.
  52. Gharachorloo, K., Gupta, A. and Hennessy, J., Two Techniques to Enhance the Performance of Memory Consistency Models, International Conference on Parallel Processing, March, 1991.
  53. Singh, J. P. and Hennessy, J. L., Data Locality and Cache Performance in the Parallel Simulation of Ocean Eddy Currents, Second International Symposium on High Performance Computing, March, 1991.
  54. Chow, F. and Hennessy, J. The Priority-based Coloring Approach to Register Allocation. ACM Transactions on Programming Languages and Systems. October, 1990.
  55. Torrellas, J., Lam, M. and Hennessy, J. L., Shared Data Placement Optimizations to Reduce Multiprocessor Cache Miss Rates, International Conference on Parallel Processing, 266-270, Pennsylvania State University. August, 1990.
  56. Gharachorloo, K., Lenoski, D., Laudon, J., Gupta, A. and Hennessy, J., Memory Consistency and Event Ordering in Scalable Shared-Memory Multiprocessors, IEEE/ACM, 17th Annual International Symposium on Computer Architecture, Seattle, WA. May, 1990. Reprinted in 25 Years of ISCA: Retrospectives and Reprints, 1998.
  57. Lenoski, D., Laudon, J., Gharachorloo, K., Gupta, A. and Hennessy, J., The Directory-Based Cache Coherence Protocol for the DASH Multiprocessor, IEEE, 17th Annual International Symposium on Computer Architecture, 148-159, Seattle, WA. May, 1990.
  58. Torrellas, J., Hennessy, J. and Weil, T., Analysis of Critical Architectural and Program Parameters in a Hierarchical Shared-Memory Multiprocessor, ACM, Sigmetrics, May, 1990.
  59. Katz, R. H. and Hennessy, J. L. “High Performance Microprocessor Architectures,” International Journal of High Speed Electronics. 1, (1): 1-18, March, 1990.
  60. Lenoski, D., Gharacharloo, K., Laudon, J., Gupta, A., Hennessy, J., Horowitz, M. and Lam, M., Design of Scalable Shared-Memory Multiprocessors: The DASH Approach, ACM, Compcon, February, 1990.
  61. Przybylski, S., Horowitz, M. and Hennessy, J., Characteristics of Performance-Optimal Multi-Level Cache Hierarchies, IEEE/ACM, 16th International Symposium on Computer Architecture, Jerusalem, Israel. June, 1989.
  62. Agarwal, A., Horowitz, M. and Hennessy, J. An Analytical Cache Model. ACM Transactions on Computer Systems. 7, (2): 184-215, May, 1989.
  63. Hennessy, J. L., RISC Architecture: A Perspective on the Past and Future, The MIT Press, Decennial Caltech VLSI Conference, 37-42, Pasadena, CA. March, 1989.
  64. Gopinath, K. and J.L. Hennessy, “Copy Elimination in Functional Languages.”  Proc. Sixteenth Annual ACM Symposium on Principles of Programming Languages, Austin, Texas, January 1989, p. 303-314.
  65. Steenkiste, P., Hennessy, J.L. A Simple Interprocedural Register Allocation Algorithm and its Effectiveness for LISP. ACM Transactions on Programming Languages and Systems, 1988.
  66. Agarwal, A., Hennessy, J.L., Horowitz, M. Cache Performance for Operating Systems and Multiprogramming Workloads. ACM Transactions on Computer Systems, 6(4):393-431, November 1988.
  67. Gross, T., Hennessy, J.L., Przybylski, S., Rowen, C. Measurement and Evaluation of the MIPS Architecture and Processor. ACM Transactions on Computer Systems, 6(3):229-257, August 1988.
  68. Gharachorloo, K., Sarkar, V., Hennessy, J.L. A Simple and Efficient Implementation Approach for Single Assignment Languages. In Lisp and Functional Programming Conference. ACM, Salt Lake City, UT, July 1988.
  69. Davis, H., Hennessy, J.L. Characterizing the Synchronization Behavior of Parallel Programs. In Symposium on Parallel Programming: Experience with Applications, Languages and Systems. ACM, New Haven, CT, July 1988.
  70. Przybylski, S., Horowitz, M., Hennessy, J.L. Performance Effects in Memory Hierarchy Design. In 15th International Symposium on Computer Architecture. IEEE, Honolulu, HI, June 1988.
  71. Agarwal, A., Simoni, R., Hennessy, J.L., Horowitz, M. An Evaluation of Directory Schemes for Cache Consistency. In 15th International Symposium on Computer Architecture. IEEE, Honolulu, HI, June 1988. Reprinted in 25 Years of ISCA: Retrospectives and Reprints, 1998.
  72. Steenkiste, P. and J.L. Hennessy, “Tags and Type Checking in Lisp: Hardware and Software Approaches.”,  Proc. Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS II), October 1987, Palo Alto, CA, pp. 50-59.
  73. Horowitz, M., Hennessy, J.L., et al. A 32b Microprocessor with On-Chip 2Kbyte Instruction Cache. In International Solid-State Circuits Conference, pp. 29-30. IEEE, February 1987.
  74. Sarkar, V., Hennessy, J.L. Partitioning Parallel Programs for Macro-Dataflow. In Symposium on LISP and Functional Programming. ACM, Boston, MA, August 1986.
  75. Steenkiste, P., Hennessy, J.L. LISP on a Reduced-Instruction-Set Processor. In Symposium on LISP and Functional Programming. ACM, Boston, MA, August 1986.
  76. McFarling, S., Hennessy, J.L. Reducing the Cost of Branches. In Proceedings 13th Symposium on Computer Architecture. IEEE/ACM, Tokyo, Japan, June 1986.
  77. Sarkar, V., Hennessy, J.L. Compile-time Partitioning and Scheduling of Parallel Program. In Symposium on Compiler Construction. ACM, Palo Alto, CA, June 1986.
  78. Rowen, C., Hennessy, J.L. SWAMI: A Flexible Logic Implementation System. In Proceedings 22nd Design Automation Conference, pp. 169-175. ACM/IEEE, June 1985.
  79. Rowen, C., Hennessy, J.L. Logic Minimization, Placement and Routing in SWAMI. In Proceedings Custom Integrated Circuits Conference. IEEE, May 1985.
  80. Hennessy, J.L. VLSI Processor Architecture. IEEE Transactions on Computers, C-33(12):1221-1246, December 1984. 25th anniversary issue; invited paper.
  81. Przybylski, S., Gross, T., Hennessy, J.L., Jouppi, N., Rowen, C. Organization and VLSI Implementation of MIPS. J. VLSI and Computer Systems 1(2):170-208, Fall 1984.
  82. Chow, F.C., Hennessy, J.L. Register Allocation by Priority-based Coloring. In Proceedings of 1984 Compiler Construction Conference. ACM, Montreal, Canada, June 1984.
  83. Rowen, C., Przybylski, S., Jouppi, N., Gross, T., Shott, J., Hennessy, J.L. MIPS: A High Performance 32-Bit NMOS Microprocessor. In Digest of International Solid-State Circuits Conference. IEEE, San Francisco, CA, February 1984.
  84. Hennessy, J.L. Partitioning Programmable Logic Arrays. In Proceedings IEEE International Conference on Computer-aided Design, pp. 180-181. IEEE, September 1983.
  85. Hennessy, J.L., Gross, T.R., Postpass Code Optimization of Pipeline Constraints. ACM Transactions on Programming Languages and Systems 5(3), July 1983.
  86. Hennessy, J.L., Jouppi, N., Przybylski, S., Rowen, C., Gross, T. Design of a High Performance VLSI Processor. In Proceedings of the Third Caltech Conference on VLSI. Calif. Institute of Technology, Pasadena, CA, March 1983.
  87. Hennessy, J.L., Jouppi, N., Przybylski, S., Rowen, C., Gross, T., Baskett, F. and J. Gill. “MIPS: A Microprocessor Architecture.” MICRO-15: Proceedings of 15th Annual Sym. on Microprogramming, 17-22, IEEE Press, Dec. 1982. Winner of the MICRO Test-of-Time Award as one of the ten most influential papers in 25 years of the symposium.
  88. Ganapathi, M., Fischer, C.N., and J.L. Hennessy. “Retargetable Compiler Code Generation.” Computing Surveys 14(4): 573-592 (1982).
  89. Hennessy, J.L., Elmquist, H. The Design and Implementation of Parametric Types in Pascal. Software: Practice and Experience 12:169-184, 1982.
  90. Hennessy, J.L., Mendelsohn, N. Compilation of the Pascal Case Statement. Software — Practice and Experience 12(19):143-154, 1982.
  91. Ganapathi, M., Fisher, C.N., Hennessy, J.L. Automatic Compiler Code Generation. Computing Surveys, December 1982.
  92. Hennessy, J.L. Symbolic Debugging of Optimized Code. ACM Transactions on Programming Languages and Systems, 4(3):323-344, July 1982.
  93. Hennessy, J.L., Jouppi, N., Baskett, F., Gross, T.R., Gill, J. Hardware/Software Tradeoffs for Increased Performance. In Symposium on Architectural Support for Programming Languages and Operating Systems. ACM, March 1982.
  94. Hennessy, J.L., Gross, T.R. Code Generation and Reorganization in the Presence of Pipeline Constraints. In Proceedings Ninth POPL Conference, pp. 120-127. ACM, January 1982.
  95. Hennessy, J.L., Kieburtz, R.B. The Formal Definition of a Real-Time Programming Language. Acta Informatica 16:309-345, 1981.
  96. Carr, R.W., Hennessy, J.L. WSCLOCK: A Simple and Effective Virtual Memory Management Algorithm. In Proceedings of Eighth Symposium on Operating Systems Principles. ACM, December 1981.
  97. Hennessy, J.L., Jouppi, N., Baskett, F., Gill, J. MIPS: A VLSI Processor Architecture. In Proceedings CMU Conference on VLSI Systems and Computations. Computer Science Press, October 1981.
  98. Hennessy, J.L. A Language for Microcode Description and Simulation in VLSI. In Proceedings of the Second Caltech Conference on VLSI. Caltech, January 1981.
  99. Hennessy, J.L. Program Optimization and Exception Handling. In Eighth POPL Proceedings, pp. 200-206. ACM, January 1981.
  100. Flynn, M.J., Hennessy, J.L. Parallelism and Representation Problems in Distributed Systems. IEEE Transactions on Computers C-29(12):1080-1086, December 1980.
  101. Flynn, M.J., Hennessy, J.L. Parallelism and Representation Problems in Distributed Systems. In Proceedings First Conference on Distributed Computing. IEEE, 1979.
  102. Hennessy, J.L., Kieburtz, R.B. A System for Producing Multitasking Software for Microprocessors. In Proceedings Meeting on Programming in the Small Processor Environment, pp. 127-134. ACM, April 1976.
  103. Hennessy, J.L., Kieburtz, R.B., Smith, D.R. TOMAL: A Task-Oriented Microprocessor Applications Language. IEEE Transactions IECI 22(8):283-289, August 1975.

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